----------------------------------------------------------------------------------
--N bits shift operation
--operation index:
--00-> sll
--01-> sla (here we assume sla is to push in a '1' while shifting left)
--10-> srl
--11-> sra
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shifter_Nbits is
    generic (N : integer);
    Port ( input : in  STD_LOGIC_VECTOR (31 downto 0);
			  operation : in STD_LOGIC_VECTOR (1 downto 0);
           enable : in  STD_LOGIC;
           output : out  STD_LOGIC_VECTOR (31 downto 0));
end shifter_Nbits;

architecture Behavioral of shifter_Nbits is
begin
	process(input,enable,operation)
	variable concat : STD_LOGIC_VECTOR ((N-1) downto 0);
	begin
		if enable = '1' then
			case operation is
				when "00" => 
					concat := (others => '0');
					output <= input((31-N) downto 0) & concat;
				when "01" => 
					concat := (others => '1');
					output <= input((31-N) downto 0) & concat;
				when "10" => 
					concat := (others => '0');
					output <= concat & input(31 downto N);
				when "11" => 
					concat := (others => input(31));
					output <= concat & input(31 downto N);
				when others =>
					output <= input;
			end case;
		else
			output <= input;
		end if;
	end process;
end Behavioral;

